ECC Working Memory System
ECC_Protected_Working_Memory
Radiation-hardened volatile working memory system with Error Correcting Code (ECC) protection providing SRAM and SDRAM for processor execution, data buffering, and real-time telemetry staging.
Purpose
Provide fast, reliable working memory for all three TMR processor modules with hardware ECC that corrects single-bit errors and detects double-bit errors caused by radiation-induced single-event upsets (SEUs). Memory scrubbing runs continuously to prevent error accumulation.
Context
Working memory is the most SEU-vulnerable component in the processing chain. Galactic cosmic rays on the lunar surface cause bit flips in SRAM and SDRAM cells. Without ECC and scrubbing, accumulated errors would corrupt flight software data within hours. Each processor module has its own independent memory bank to maintain TMR isolation, with shared memory regions accessible only through the voted output path.
Principles
- ▸SECDED (Single Error Correct, Double Error Detect) ECC on all memory words
- ▸Continuous background memory scrubbing to prevent multi-bit error accumulation
- ▸Each TMR processor module has independent memory bank for fault isolation
- ▸EDAC (Error Detection and Correction) counters track SEU rates for health monitoring
- ▸Memory parity and ECC checking on every read access with hardware correction
Typical implementations
- ▸Cobham/Aeroflex UT8R512K 512Kx8 radiation-hardened SRAM (300 krad TID)
- ▸3D-Plus 3DSR4M16VS8164 rad-hard stacked SDRAM modules
- ▸BAE Systems radiation-hardened DDR SDRAM controller IP
- ▸MRAM (Magnetoresistive RAM) for critical configuration data (inherently SEU immune)
Lunar considerations
- ▸SEU rate on lunar surface approximately 10x higher than LEO due to no geomagnetic shielding
- ▸Memory scrub rate must exceed SEU accumulation rate to prevent uncorrectable errors
- ▸Thermal cycling affects memory module solder joints and wire bonds over decades
- ▸MRAM cells provide inherently radiation-hard non-volatile configuration storage
Specifications
Functional
| primary function | Provide ECC-protected volatile working memory for TMR processor array execution and data buffering |
| inputs | Read/write requests from L3-CDH-PROC-CPU modules, Memory scrub commands from flight software, ECC configuration parameters, Data from L2-CDH-BUS for DMA transfers |
| outputs | ECC-corrected data to processor modules, EDAC error count telemetry (corrected and uncorrectable), Memory health status and utilization metrics, DMA transfer completions to bus interface |
| capacity per module mb | 512 |
| total capacity mb | 2048 |
| access time ns | 15 |
| bandwidth gbps | 6.4 |
| ecc correction | SECDED |
| scrub rate mb per s | 100 |
| seu threshold per day | 0.1 |
Physical
| mass kg | 3.0 |
| dimensions | Memory modules integrated on processor boards, 0.08m x 0.06m per bank |
| materials | Radiation-hardened SRAM and SDRAM dies in ceramic packages, 3D-Plus stacked memory module encapsulation, Controlled-impedance memory bus traces on polyimide PCB, Conformal coating (Parylene-C) for moisture and particle protection |
| operating temp c | -40 to +85 |
| survival temp c | -55 to +125 |
| radiation tolerance krad | 300 |
| seu cross section cm2 bit | 1e-14 |
| vacuum compatible | True |
Operational
| power consumption w | 8 |
| thermal range c | -40, 85 |
| lifetime years | 100 |
| mtbf hours | 300000 |
Interfaces
Provides
- Read/write memory interface with transparent hardware ECC correction on every access.
- EDAC error counters, scrub status, and memory utilization metrics for system health monitoring.
Requires
- Address, data, and control bus from processor for memory read/write operations.
- 3.3V and 1.8V regulated power for SRAM and SDRAM with low noise requirements.
Cite this entry
Lunar Ark Codex. "ECC Working Memory System" (L3-CDH-PROC-MEM). Retrieved 10 September 2026, from https://lunarark.com/entry/L3-CDH-PROC-MEM
Licensed CC-BY-SA 4.0. You may reuse and adapt this entry with attribution, under the same licence.