Supercapacitor Controller
FPGA-Based Fast Transient Controller with ESR Diagnostics
Rad-tolerant FPGA-based controller running sub-millisecond control loops for the bidirectional DC-DC, voltage balancer, and rack telemetry — supporting transient detection on the main bus and fast supercap response within a few hundred microseconds.
Purpose
Provide the fast-loop response that distinguishes supercap storage from batteries; detect bus voltage deviations, command the DC-DC to inject/absorb current, and maintain SOC within optimal operating window.
Context
Embedded in the supercap subsystem; takes high-level setpoints from L2-ESS-MGMT and operates autonomously on sub-second timescales. Talks to L3-ESS-SCAP-DCDN (DC-DC), L3-ESS-SCAP-BAL (balancer), L3-ESS-SCAP-RACK (telemetry).
Principles
- ▸FPGA-based control allows >100 kHz loop rates needed for fast power electronics
- ▸Bus voltage deviation triggers supercap injection within microseconds — proportional-integral control with feed-forward
- ▸ESR (equivalent series resistance) measured via voltage drop / current ratio; rise indicates aging
- ▸Self-discharge top-up logic periodically replenishes lost charge to maintain SOC
- ▸Coordination with L3-ESS-LITH-BMS prevents simultaneous discharge race conditions
- ▸Brownout / blackout ride-through protocols engage automatically on bus voltage collapse
Typical implementations
- ▸Microchip RTG4 FPGA (rad-tolerant) running VHDL state machines
- ▸Texas Instruments F28 series real-time DSPs (terrestrial)
- ▸Spacecraft power-system FPGAs (proprietary, used on ISS, GEO comsats)
Lunar considerations
- ▸Fast control loops cannot be implemented on rad-hard CPU due to clock-rate limits; FPGA fabric required
- ▸TMR FPGA logic protects against SEUs during high-rate switching
- ▸Health telemetry updates on slower (10 Hz) loop to L1-CDH
- ▸Predictive control models bus load patterns to anticipate transients
- ▸Updates over authenticated DTN with rollback on failed verification
Specifications
Functional
| primary function | Real-time control of supercap subsystem |
| inputs | Bus voltage from L1-PDM, Supercap rack voltage from L3-ESS-SCAP-RACK, Cell voltages from L3-ESS-SCAP-MOD, Setpoints from L2-ESS-MGMT |
| outputs | Current setpoint to L3-ESS-SCAP-DCDN, Balancing enable / current targets to L3-ESS-SCAP-BAL, SOC / SOH / ESR telemetry to L2-ESS-MGMT, Trip signals to L3-ESS-SCAP-DCDN on safety violation |
| control loop rate khz | 10 |
| telemetry rate hz | 100 |
| soc estimation error percent | 1 |
| esr estimation error percent | 5 |
| fpga redundancy | TMR with majority voting |
Physical
| mass kg | 1.0 |
| dimensions | 180 × 120 × 30 mm 3U cPCI card |
| materials | Microchip RTG4 FPGA, Rad-hard SRAM with EDAC, Polyimide PCB, Aluminum chassis |
| operating temperature c | -40, 70 |
| radiation tid krad | 100 |
| seu let threshold mev cm2 per mg | 37 |
Operational
| power consumption w | 6 |
| thermal range c | -40, 70 |
| lifetime years | 25 |
| mtbf hours | 300000 |
Interfaces
Provides
- Current/power setpoints
- Balancing enable / targets
- Aggregated SOC/SOH/ESR/health
Requires
- Rack telemetry
- Cell voltages
- Bus voltage measurement
Cite this entry
Lunar Ark Codex. "Supercapacitor Controller" (L3-ESS-SCAP-CTRL). Retrieved 10 September 2026, from https://lunarark.com/entry/L3-ESS-SCAP-CTRL
Licensed CC-BY-SA 4.0. You may reuse and adapt this entry with attribution, under the same licence.