L3-DVT-DIGI-ECC
CRITICAL
COMMAND CONTROL
Level 3 · hardware
ECC Engine
BCH / LDPC Error-Correcting Code Engine
Hardware-accelerated BCH and LDPC error-correcting code engine providing bit-level error correction across stored data.
Purpose
Hardware-accelerated BCH and LDPC error-correcting code engine providing bit-level error correction across stored data.
Context
Child of L2-DVT-DIGI within the Lunar Ark system
Principles
- ▸BCH codes for cell-level NAND ECC
- ▸LDPC for higher-density inner code
- ▸Hardware-accelerated decode via FPGA
- ▸Per-page error statistics tracked
- ▸Long-mission ECC tuning as cells age
Typical implementations
- ▸Industrial flash ECC (Marvell, Phison)
- ▸NASA spacecraft ECC heritage
- ▸ESA storage ECC
Lunar considerations
- ▸ECC algorithms tracked with age via L3-DVT-INTEG
- ▸Long-mission tuning
- ▸Rad-tolerant FPGA implementation
Specifications
Functional
| primary function | Hardware-accelerated BCH and LDPC error-correcting code engine providing bit-level error correction across stored data. |
| correction capability bits | 80 |
Physical
| mass kg | 0 |
| materials | Rad-hard FPGA fabric, BCH/LDPC IP cores |
| vacuum compatibility | True |
Operational
| power consumption w | 2 |
| thermal range c | -40, 70 |
| lifetime years | 100 |
| mtbf hours | 500000 |
Interfaces
Provides
- ECC-corrected read data
- Error statistics
Requires
- Raw page reads
Cite this entry
Lunar Ark Codex. "ECC Engine" (L3-DVT-DIGI-ECC). Retrieved 10 September 2026, from https://lunarark.com/entry/L3-DVT-DIGI-ECC
Licensed CC-BY-SA 4.0. You may reuse and adapt this entry with attribution, under the same licence.